1. Field of Invention
This invention relates to a voltage-to-current converter which makes it possible to control conversion of a voltage to a current by means of the size of a transistor irrespective of a supply voltage, an input voltage, and fabrication conditions of a transistor.
2. Description of the Prior Art
FIG. 1 of the drawings hereof is a detailed circuit diagram of a circuit provided with a conventional voltage-to-current converter which is used as a constant-current source by providing a constant-voltage source to an input voltage terminal V.sub.IN of this circuit, the converter also being useful in various circuits, when an analog circuit is used for an integrated circuit.
As shown in FIG. 1, the conventional voltage-to-current converter comprises an operational amplifier 10 for receiving a constant-voltage source V.sub.IN to a noninverting terminal, and amplifying the voltage; and a constant-current source generating circuit 20 for receiving an output voltage of the operational amplifier 10 as an input, and converting the inputted voltage to a constant-current I.sub.OUT.
The constant-current source generating circuit 20 includes a converting circuit 21 for receiving the output voltage of the operational amplifier 10 as an input, and converting the inputted voltage to a current; a current mirror 22 for receiving the output current of the converting circuit 21, and enabling the transistors M2 and M3 to pass current of similar value; and
an output current mirror 23 for biasing the voltage of a drain terminal of the transistor M3 with a predetermined value, to constantly maintain the current flowing out from the current mirror 22.
The converting circuit 21 includes an n-channel transistor M1 of which drain terminal is connected with a drain terminal a of the transistor M2 of the current mirror 22, and of which gate and source terminals are respectively connected with an output terminal b and an inverting terminal (-) of the operational amplifier 10; and a resistor R1 for connecting a source terminal of the transistor M1 to a ground terminal V.sub.SS.
The current mirror 22 includes p-channel transistors M2 and M3 for applying a supply voltage V.sub.DD to a common source terminal, having a common gate terminal, and connecting the common gate terminal to the drain terminal a of the transistor M2; and a p-channel transistor M4 for connecting the source terminal with a drain terminal c of the transistor M3, and connecting a gate terminal with a gate terminal b of the transistor M1 of the converting circuit 21.
The output current mirror 23 includes an n-channel transistor MS having a drain terminal connected to the drain terminal of the transistor M4 of the current mirror 22, connecting between drain terminal and gate terminal, and connecting a source terminal to the ground terminal V.sub.SS ; and an n-channel transistor M6 for connecting a drain terminal to the output terminal I.sub.OUT of the constant-current source, connecting a gate terminal to the gate terminal of the transistor M5, and connecting a source terminal to the ground terminal V.sub.SS.
A conversion equation to be achieved by the above-identified conventional voltage-to-current converter is as follows: EQU I.sub.OUT =K.times.(V.sub.IN /R1) (1)
By the operational amplifier 10 of the conventional voltage-to-current converter shown in FIG. 1, the resistor R1 of the converting circuit 21 has the input voltage V.sub.IN. By this voltage V.sub.IN, the current value of the n-channel transistor M1 is V.sub.IN /R1 which also flows to the p-channel transistor M2 of the current mirror 22.
An equation showing a drain current of a MOSFET is as follows: EQU i.sub.D =K(V.sub.GS -V.sub.T).sup.2 (1+.lambda.V.sub.DS) (2)
Where, i.sub.D is the drain current of the MOSFET;
V.sub.GS is the gate-to-source voltage of the MOSFET;
V.sub.DS is the drain-to-source voltage of the MOSFET;
V.sub.T is the threshold voltage of the MOSFET;
K is a proportional constant related to the size of the MOSFET; and
.lambda. is a proportional constant related to both the size of the MOSFET and to the electric potential of the substrate of the MOSFET, namely, channel length modulation factor.
In the constant-current source generating circuit 20, the current mirror 22 enables the transistors M2 and M3 to flow current of a similar value, respectively, by making common gate and source terminals. According to equation (2), the current mirror 22 determines the current of both transistor by means of the gate-to-source voltage V.sub.GS and the drain-to-source voltage V.sub.DS.
Consequently, in order to maintain the same current for the two transistors, the same voltage should be maintained for the gate-to-source voltage V.sub.GS and the drain-to-source voltage V.sub.DS. In addition, as shown in equation (2), the current ratio of the two transistors of the current mirror 22 is determined by the proportional constant K related to the size of the MOSFET.
In the transistor M2 of the current mirror 22, the gate terminal is connected to the drain terminal. Accordingly, the gate-to-source voltage V.sub.GS is identical with the drain-to-source terminal V.sub.DS. Further, by constantly determining the gate-to-source voltage V.sub.GS with respect to the drain current i.sub.D, the voltage applied to the terminal a of the the transistor M2 is determined by the drain current i.sub.D as a constant value.
Meanwhile, to maintain the constant current ratio of the transistors M2 and M3 in the current mirror 22, the voltage of the drain terminal a of the transistor M2 should be identical with that of the drain terminal c of the transistor M3.
For the above purpose, the transistor M4 of the current mirror 22 has a function of biasing the voltage of the drain terminal c of the transistor M3 by a constant value.
In addition, the gate terminal b of the transistors M1 and M4 of the constant-current source generating circuit 20 is biased for applying a gate-to-source voltage V.sub.GS1 that is suitable for flowing of the drain current i.sub.D by the transistor M1. Accordingly, the gate terminals of the transistors M1 and M4 have a voltage determined by adding the input voltage V.sub.IN to the gate-to-source voltage V.sub.GS1.
The voltage applied to the drain terminal c of the transistor M3 of the current mirror 22 is added to the gate-to-source voltage .vertline.V.sub.GS4 .vertline. of the transistor M4 in the terminal b of the transistors M1 and M4. The voltage is described in the following equation (3): EQU V(c)=V.sub.IN +V.sub.GS1 +.vertline.V.sub.GS4 .vertline. (3)
Where, V(c) is an electric potential of node c.
At this time, the gate-to-source voltage V.sub.GS1 of the transistor M1 is larger than the threshold voltage V.sub.T1 of the transistor M1, and the gate-to-source voltage .vertline.V.sub.GS4 .vertline. of the transistor M4 is larger than the threshold voltage V.sub.T4 of the transistor M4.
Through the operation of the above-described conventional voltage-to-current converter, as shown in equation (3), since the node c has a varied voltage according to the input voltage V.sub.IN, the transistors M2 and M3 of the current mirror 22 do not maintain the same current continuously. Accordingly, in case the input voltage V.sub.IN is varied, the conventional voltage-to-current converter has a problem, generating an error in the conversion equation (1).
FIG. 2 is the resulting graph of a simulation showing the variation of the output current I.sub.OUT in accordance with the input voltage V.sub.IN of the conventional voltage-to-current converter of FIG. 1.
As shown in FIG. 2, the actual result of the computer simulation has some errors, contrary to variation characteristics of the ideal output voltage V.sub.OUT with respect to the variation of the input voltage V.sub.IN calculated through the conversion equation in equation (1).
Also, as is widely known, in case the conventional voltage-to-current converter is embodied as an integrated circuit, the threshold voltage V.sub.T of the MOSFET may show a deviation according to the type of chip. In this case, the electric potential of the node c described in the equation (3) may sensitively vary according to both the fabrication method of the chip and the supply voltage V.sub.DD.
FIG. 3 is the resulting graph of a simulation showing the variation of the output current I.sub.OUT in accordance with both the supply voltage V.sub.DD and the threshold voltage V.sub.T of the conventional voltage-to-current converter.
In the simulation graph shown in FIG. 3, the X-axis shows the supply voltage V.sub.DD, each line plotted on the graph shows an actual result when the threshold voltage V.sub.T is varied by a small increment.
Since the input voltage V.sub.IN is 1.2 V and the resistor R1 is 600 K.OMEGA., the ideal output current I.sub.OUT calculated through the conversion equation (1) is 200 .mu.A. However, the actual simulation result has a number of errors compared with the above ideal current I.sub.OUT.